Control Unit Operation

Micro-Operations

•A computer executes a program

•Fetch/execute cycle

•Each cycle has a number of steps see pipelining

•Called micro-operations

•Each step does very little

•Atomic operation of CPU

Fetch - 4 Registers

•Memory Address Register (MAR)
Connected to address bus
Specifies address for read or write op
•Memory Buffer Register (MBR)
—Connected to data bus
Holds data to write or last data read
•Program Counter (PC)
Holds address of next instruction to be fetched
•Instruction Register (IR)
Holds last instruction fetched

Fetch Sequence

•Address of next instruction is in PC
•Address (MAR) is placed on address bus
•Control unit issues READ command
•Result (data from memory) appears on data bus
•Data from data bus copied into MBR
•PC incremented by 1 (in parallel with data fetch from memory)
•Data (instruction) moved from MBR to IR
•MBR is now free for further data fetches 

Fetch Sequence (symbolic) 
•t1:  MAR <- (PC)
•t2:  MBR <- (memory)
•   PC <- (PC) +1
•t3:  IR <- (MBR)
•(tx = time unit/clock cycle)
•or
•t1:  MAR <- (PC)
•t2:  MBR <- (memory)
•t3:  PC <- (PC) +1
•  IR <- (MBR) 

Rules for Clock Cycle Grouping 
•Proper sequence must be followed
—MAR <- (PC) must precede MBR <- (memory)
•Conflicts must be avoided
—Must not read & write same register at same time
—MBR <- (memory) & IR <- (MBR) must not be in same cycle
•Also:  PC <- (PC) +1 involves addition
—Use ALU
—May need additional micro-operations 


Indirect Cycle 
•MAR <- (IRaddress)  -  address field of IR 
•MBR <- (memory) 
•IRaddress <- (MBRaddress)
•MBR contains an address 
•IR is now in same state as if direct addressing had been used 
•(What does this say about IR size?)  

Interrupt Cycle 
•t1:  MBR <-(PC)
•t2:  MAR <- save-address
•   PC <- routine-address
•t3:  memory <- (MBR)
•This is a minimum
—May be additional micro-ops to get addresses
—N.B. saving context is done by interrupt handler routine, not micro-ops 

Execute Cycle (ADD) 
•Different for each instruction
•e.g. ADD R1,X - add the contents of location X to Register 1 , result in R1
•t1:  MAR <- (IRaddress)
•t2:  MBR <- (memory)
•t3:  R1 <- R1 + (MBR)
•Note no overlap of micro-operations 

Execute Cycle (ISZ) 
•ISZ X - increment and skip if zero
—t1:  MAR <- (IRaddress)
—t2:  MBR <- (memory)
—t3:  MBR <- (MBR) + 1
—t4:  memory <- (MBR)
—   if (MBR) == 0 then PC <- (PC) + 1

•Notes:
—if is a single micro-operation
—Micro-operations done during t4 

Execute Cycle (BSA) 
•BSA X - Branch and save address
—Address of instruction following BSA is saved in —Execution continues from X+1 
—t1:  MAR <- (IRaddress)
—   MBR <- (PC)
—t2:  PC <- (IRaddress)
—   memory <- (MBR)
—t3:  PC <- (PC) + 1